module tb_mux_2_to_1;
	reg  	a,b,sel;
	wire 	out,outbar;
	
	mux_2_to_1 dut(a,b,out,outbar,sel);
	
initial
	begin
		a = 1'b1;
		b = 1'b0;
		#50;
		sel = 1'b1;
		#50
		sel = 1'b0;
		#100
		b = 1'b1;
	end 
endmodule
